photos:Challenge L
Inspection of daddys new toy
Date: 2010:02:03 18:15:53 		Challenge DM restriction 'screw'
Date: 2010:02:24 22:06:52 		Screw removed. Now unlocked
Date: 2010:02:24 22:20:30 		Test run with 12 CPUs
Date: 2010:03:04 22:38:45
Original drive backplane configuration
Date: 2010:03:22 21:26:58 		Both SCSI channels modified to SE mode
Date: 2010:03:22 21:29:35 		Original IO4 configuration
Date: 2010:03:22 21:41:49 		Modified IO4 configuration
Date: 2010:03:22 21:49:52
IO4 with Prisa NetFX and S2 SCSI mezz
Date: 2010:03:22 21:56:18 		R10000 CPU with 2MB L2 cache
Date: 2010:03:22 22:03:54 		IP25 board with quad R10000 CPUs
Date: 2010:03:22 22:05:02 		Finished system
Date: 2010:04:13 21:52:34
A view of the scsi box
Date: 2010:04:13 21:53:14 		No guts, no glory
Date: 2010:04:13 21:55:06 		More modern harddisk
Date: 2010:04:13 22:01:08

Hardware inventory, not final: 
IRIS 6# hinv -v
CPU Board at Slot 2: (Enabled)
  Processor 0 at Slot 2/Slice 0: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
  Processor 1 at Slot 2/Slice 1: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
  Processor 2 at Slot 2/Slice 2: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
  Processor 3 at Slot 2/Slice 3: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
CPU Board at Slot 3: (Enabled)
  Processor 4 at Slot 3/Slice 0: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
  Processor 5 at Slot 3/Slice 1: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
  Processor 6 at Slot 3/Slice 2: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
  Processor 7 at Slot 3/Slice 3: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.6
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
CPU Board at Slot 4: (Enabled)
  Processor 8 at Slot 4/Slice 0: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.5
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
  Processor 9 at Slot 4/Slice 1: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.5
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
  Processor 10 at Slot 4/Slice 2: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.5
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
  Processor 11 at Slot 4/Slice 3: 194 Mhz R10000 with 2 MB secondary cache
(Enabled)
CPU: MIPS R10000 Processor Chip Revision: 2.5
FPU: MIPS R10010 Floating Point Chip Revision: 0.0
Secondary unified instruction/data cache size: 2 Mbytes
Data cache size: 32 Kbytes
Instruction cache size: 32 Kbytes
Main memory size: 2048 Mbytes, 2-way interleaved
MC3 Memory Board at Slot 1: 2048 MB of memory (Enabled)
  Bank A contains 64 MB SIMMS (Enabled)
  Bank B contains 64 MB SIMMS (Enabled)
  Bank C contains 64 MB SIMMS (Enabled)
  Bank D contains 64 MB SIMMS (Enabled)
  Bank E contains 64 MB SIMMS (Enabled)
  Bank F contains 64 MB SIMMS (Enabled)
  Bank G contains 64 MB SIMMS (Enabled)
  Bank H contains 64 MB SIMMS (Enabled)
I/O board, Ebus slot 5: IO4 revision 1
Integral EPC serial ports: 4
Integral Ethernet controller: et0, Ebus slot 5
EPC external interrupts
Integral SCSI controller 1: Version WD33C95A, differential, revision 0
  Disk drive: unit 1 on SCSI controller 1
Integral SCSI controller 0: Version WD33C95A, single ended, revision 0
  Tape drive: unit 6 on SCSI controller 0: 8mm(8500) cartridge
  CDROM: unit 4 on SCSI controller 0
CC synchronization join counter
Integral EPC parallel port: Ebus slot 5
VME bus: adapter 0 mapped to adapter 21
VME bus: adapter 21
IRIS 7#
Album created by album generator from Marginal Hacks by Dave on Sat Jan 8 20:54:15 2011